In memory access control of a multi-bank memory having a plurality of banks such as SDRAM (Synchronous Dynamic Random Access Memory) etc., an arbitration circuit using a priority control register can be used to arbitrate a memory request instruction from a plurality of CPUs and IO devices. In the circuit, a plurality of memory requests are allocated for each requested bank to a queue called a request buffer and are held. Then, the memory requests are read from the respective request buffers in order sequentially from the highest priority based on the priorities of the memory requests stored in a priority control register and are processed. In the control system, when the priority of the memory request of a request buffer becomes the highest and processed, the priority of the request buffer is defined as the lowest priority in the next instruction execution cycle. On the other hand, in the next instruction execution cycle the request buffer from which an instruction has been least recently read becomes the highest priority, and the memory request read from the request buffer is processed. This control system is what is called an LRU (least recently used) control system.
An access regulation is used for the DRAM. The access regulation is a regulation according to which, for example, when a data read request is processed for the DRAM in an instruction execution cycle, and when a data write request (different instruction) is next processed, for example, processes are to be kept waiting for seven cycles. Otherwise, when a data read request is processed on a bank in the DRAM in an instruction execution cycle, and when a data read request (identical instruction) is next processed on another bank, processes are to be kept waiting for two cycles, for example.
Assume that, in the conventional technology of memory access control using the priority control register, a memory request A read from one request buffer selected based on the priorities of the memory requests stored in the priority control register does not satisfy the access regulation of the DRAM. In this case, the process of the memory request A is kept waiting until the instruction execution cycle in which the access regulation is satisfied.
However, in the request buffers not selected based on the priorities of the memory requests stored in the priority control register, there can be a request buffer from which a memory request satisfying an access regulation is read. For example, when the memory request currently being processed is a data read request, and when the memory request selected in the next instruction execution cycle is a data write request, the data write request has to be kept waiting for seven cycles, for example, from the execution start of the data read request. In this example, it is assumed that there is another data read request to the execution bank different from the execution bank of the preceding data read request in the request buffers not selected by the priority control register. In this case, since the wait cycle for an identical instruction can be shorter than the wait cycle for a different instruction, the other data read request described above can be processed after, for example, three cycles from the execution start of the preceding data read request.
In this case, the memory request B which is in another request buffer and satisfies the access regulation cannot be conventionally processed until the memory request A (different instruction) currently being read from the request buffer by the priority control register is processed. That is, in the conventional technology of the memory access control using a priority control register, there is the problem that the efficiency of execution of a memory request is degraded in the case above.                Patent Document 1: Japanese Laid-open Patent Publication No. 6-161941        Patent Document 2: Japanese Laid-open Patent Publication No. 11-272567        Patent Document 3: Japanese Laid-open Patent Publication No. 2005-173859        Patent Document 4: Japanese Laid-open Patent Publication No. 2008-503808        